RISC-V Microprocessor System-On-Chip Design is written to be accessible to an advanced undergraduate audience with limited background. It explains concepts from operating systems, VLSI, and memory systems as necessary, and High school mathematics is sufficient preparation for most of the book, although the floating point and division chapters will be primarily of interest to those with a curiosity about computer arithmetic. Like Harris and Harris’s Digital Design and Computer Architecture textbooks, this book will appeal to students with easy-to-read and complete explanations, sidebars, and occasional humor and cartoons.
It comes with an open-source implementation and will include end-of-chapter problems to extend the RISC-V processor in various ways. Ancillary materials include a GitHub repository with complete open-source SystemVerilog code, validation code in C and assembly language, and code for benchmarking and booting Linux.
1. 2. Introduction to RISC-V - p. 31 2. 3. RISC-V Software Tool Flow - p. 89 3. 4. HDL Design Practices - p. 141 4. 5. Design Verification - p. 193 5. 6. Logic Synthesis - p. 249 6. 7. Pipelined Core - p. 299 7. 8. Privileged Operations - p. 335 8. 9. Bus Interface - p. 383 9. 10. Caches - p. 429 10. 11. Memory Management Unit - p. 469 11. 12. Load/Store Unit - p. 515 12. 13. Instruction Fetch Unit - p. 545 13. 14. Extensions: C (Compressed) - p. 579 14. 15. Extensions: M (Multiply and Divide) - p. 591 15. 16. Extensions: F/D/Q/Zfh/Zfa (Floating-Point) - p. 617 16. 17. Extensions: A (Atomic) - p. 673 17. 18. Extensions: Zb∗ & Zk∗ (Bit Manipulation and Cryptography) - p. 715 18. 19. Other Extensions - p. 767 19. 20. Peripherals - p. 784.e1 20. 21. Benchmarking - p. 784.e24 21. 22. Linux - p. 784.e48 22. 23. FPGA Implementation - p. 784.e78 23. A. Wally Synopsis - p. 784.e106 24. B. Hitchhiker’s Guide to Linux - p. 784.e153 25. C. Version Control Using Git - p. 784.e170 26. D. Tcl Book of Armaments - p. 784.e185 27. F. Floating-Point Implementation - p. 784.e193 28. F.1 Fused Multiply-Add - p. 784.e193 29. F.1.1 Multiply Significands - p. 784.e193 30. F.1.2 Product and Addend Signs - p. 784.e193 31. F.1.3 Add Exponents - p. 784.e193 32. F.1.4 Alignment Shift - p. 784.e194 33. F.1.5 Add Aligned Significands - p. 784.e195 34. F.1.6 LZA: Leading Zero Anticipator - p. 784.e198 35. F.1.7 Multipath FMA Optimization - p. 784.e200 36. F.2.1 Recurrence Division Algorithm - p. 784.e202 37. F.2.2 Radix-2 Recurrence Division - p. 784.e207 38. F.2.3 Radix-4 Recurrence Division - p. 784.e213 39. F.2.3.1 Example - p. 784.e217 40. F.2.3.2 Radix-4 Implementation - p. 784.e217 41. F.2.4 Divider Latency - p. 784.e219 42. F.2.5 Quotient Conversion - p. 784.e220 43. F.2.6 Early Termination - p. 784.e222 44. F.2.7 Subnormal Floating-Point Preprocessing - p. 784.e223 45. F.2.8 Floating-Point Postprocessing - p. 784.e224 46. F.2.9 Integer Division - p. 784.e225 47. F.2.10 Square Root - p. 784.e234 48. F.2.10.1 Recurrence Algorithm - p. 784.e235 49. F.2.10.2 Containment of Residual - p. 784.e236 50. F.2.10.3 Radix-2 Square Root Digit Selection - p. 784.e238 51. F.2.10.4 Radix-4 Square Root Digit Selection - p. 784.e238 52. F.2.10.5 Addend Input Selection - p. 784.e239 53. F.2.10.6 On-the-Fly Conversion - p. 784.e242 54. F.2.10.7 Early Termination - p. 784.e243 55. F.2.10.8 Radix-2 Example - p. 784.e244 56. F.2.10.9 Radix-2 Implementation - p. 784.e246 57. F.2.10.10 Radix-4 Example - p. 784.e246 58. F.2.10.11 Radix-4 Implementation - p. 784.e248 59. F.2.10.12 Floating-Point Square Root Postprocessing - p. 784.e248 60. F.2.11 Unified Divide and Square Root - p. 784.e249 61. F.2.12 Multiplicative Algorithms for Division and Square Root - p. 784.e257 62. F.3.1 Result Exponent - p. 784.e258 63. F.3.2 Shift Amount Selection - p. 784.e261 64. F.3.3 Examples - p. 784.e262 65. F.4.1 Shift Calculation - p. 784.e263 66. F.4.2 Initial Result Mux - p. 784.e265 67. F.4.3 Normalization Shift - p. 784.e265 68. F.4.4 Correction Shift - p. 784.e265 69. F.4.5 Sign Logic - p. 784.e267 70. F.4.6 Rounding - p. 784.e268 71. F.4.7 Special Cases and Flags - p. 784.e269 72. Bibliography - p. 785 73. Index - p. 799 74. RISC-V Instruction Set Summary - p. 815
RISC-V Microprocessor System-On-Chip Design is written to be accessible to an advanced undergraduate audience with limited background. It explains concepts from operating systems, VLSI, and memory systems as necessary, and High school mathematics is sufficient preparation for most of the book, although the floating point and division chapters will be primarily of interest to those with a curiosity about computer arithmetic. Like Harris and Harris’s Digital Design and Computer Architecture textbooks, this book will appeal to students with easy-to-read and complete explanations, sidebars, and occasional humor and cartoons.
It comes with an open-source implementation and will include end-of-chapter problems to extend the RISC-V processor in various ways. Ancillary materials include a GitHub repository with complete open-source SystemVerilog code, validation code in C and assembly language, and code for benchmarking and booting Linux.
1. 2. Introduction to RISC-V - p. 31 2. 3. RISC-V Software Tool Flow - p. 89 3. 4. HDL Design Practices - p. 141 4. 5. Design Verification - p. 193 5. 6. Logic Synthesis - p. 249 6. 7. Pipelined Core - p. 299 7. 8. Privileged Operations - p. 335 8. 9. Bus Interface - p. 383 9. 10. Caches - p. 429 10. 11. Memory Management Unit - p. 469 11. 12. Load/Store Unit - p. 515 12. 13. Instruction Fetch Unit - p. 545 13. 14. Extensions: C (Compressed) - p. 579 14. 15. Extensions: M (Multiply and Divide) - p. 591 15. 16. Extensions: F/D/Q/Zfh/Zfa (Floating-Point) - p. 617 16. 17. Extensions: A (Atomic) - p. 673 17. 18. Extensions: Zb∗ & Zk∗ (Bit Manipulation and Cryptography) - p. 715 18. 19. Other Extensions - p. 767 19. 20. Peripherals - p. 784.e1 20. 21. Benchmarking - p. 784.e24 21. 22. Linux - p. 784.e48 22. 23. FPGA Implementation - p. 784.e78 23. A. Wally Synopsis - p. 784.e106 24. B. Hitchhiker’s Guide to Linux - p. 784.e153 25. C. Version Control Using Git - p. 784.e170 26. D. Tcl Book of Armaments - p. 784.e185 27. F. Floating-Point Implementation - p. 784.e193 28. F.1 Fused Multiply-Add - p. 784.e193 29. F.1.1 Multiply Significands - p. 784.e193 30. F.1.2 Product and Addend Signs - p. 784.e193 31. F.1.3 Add Exponents - p. 784.e193 32. F.1.4 Alignment Shift - p. 784.e194 33. F.1.5 Add Aligned Significands - p. 784.e195 34. F.1.6 LZA: Leading Zero Anticipator - p. 784.e198 35. F.1.7 Multipath FMA Optimization - p. 784.e200 36. F.2.1 Recurrence Division Algorithm - p. 784.e202 37. F.2.2 Radix-2 Recurrence Division - p. 784.e207 38. F.2.3 Radix-4 Recurrence Division - p. 784.e213 39. F.2.3.1 Example - p. 784.e217 40. F.2.3.2 Radix-4 Implementation - p. 784.e217 41. F.2.4 Divider Latency - p. 784.e219 42. F.2.5 Quotient Conversion - p. 784.e220 43. F.2.6 Early Termination - p. 784.e222 44. F.2.7 Subnormal Floating-Point Preprocessing - p. 784.e223 45. F.2.8 Floating-Point Postprocessing - p. 784.e224 46. F.2.9 Integer Division - p. 784.e225 47. F.2.10 Square Root - p. 784.e234 48. F.2.10.1 Recurrence Algorithm - p. 784.e235 49. F.2.10.2 Containment of Residual - p. 784.e236 50. F.2.10.3 Radix-2 Square Root Digit Selection - p. 784.e238 51. F.2.10.4 Radix-4 Square Root Digit Selection - p. 784.e238 52. F.2.10.5 Addend Input Selection - p. 784.e239 53. F.2.10.6 On-the-Fly Conversion - p. 784.e242 54. F.2.10.7 Early Termination - p. 784.e243 55. F.2.10.8 Radix-2 Example - p. 784.e244 56. F.2.10.9 Radix-2 Implementation - p. 784.e246 57. F.2.10.10 Radix-4 Example - p. 784.e246 58. F.2.10.11 Radix-4 Implementation - p. 784.e248 59. F.2.10.12 Floating-Point Square Root Postprocessing - p. 784.e248 60. F.2.11 Unified Divide and Square Root - p. 784.e249 61. F.2.12 Multiplicative Algorithms for Division and Square Root - p. 784.e257 62. F.3.1 Result Exponent - p. 784.e258 63. F.3.2 Shift Amount Selection - p. 784.e261 64. F.3.3 Examples - p. 784.e262 65. F.4.1 Shift Calculation - p. 784.e263 66. F.4.2 Initial Result Mux - p. 784.e265 67. F.4.3 Normalization Shift - p. 784.e265 68. F.4.4 Correction Shift - p. 784.e265 69. F.4.5 Sign Logic - p. 784.e267 70. F.4.6 Rounding - p. 784.e268 71. F.4.7 Special Cases and Flags - p. 784.e269 72. Bibliography - p. 785 73. Index - p. 799 74. RISC-V Instruction Set Summary - p. 815
