Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more than twice as much new content, adding the latest developments in circuit models, temperature considerations, power management, memory issues, and heterogeneous integration. 3-D IC experts Pavlidis, Savidis, and Friedman cover the full product development cycle throughout the book, emphasizing not only physical design, but also algorithms and system-level considerations to increase speed while conserving energy. A handy, comprehensive reference or a practical design guide, this book provides effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits.
Expanded with new chapters and updates throughout based on the latest research in 3-D integration:
1. Chapter 1. Introduction - p. 1 2. Chapter 2. Manufacturing of Three-Dimensional Packaged Systems - p. 15 3. Chapter 3. Manufacturing Technologies for Three-Dimensional Integrated Circuits - p. 37 4. Chapter 4. Electrical Properties of Through Silicon Vias - p. 67 5. Abstract - p. 67 6. 4.1 Physical Characteristics of a Through Silicon Via - p. 69 7. 4.2 Electrical Model of Through Silicon Via - p. 70 8. 4.3 Modeling a Three-Dimensional Via as a Cylinder - p. 71 9. 4.4 Compact Models - p. 73 10. 4.5 Through Silicon Via Impedance Models - p. 82 11. 4.6 Electrical Characterization Through Numerical Simulation - p. 105 12. 4.7 Case Study—Through Silicon Via Characterization of the MITLL TSV process - p. 107 13. 4.8 Summary - p. 116 14. Chapter 5. Substrate Noise Coupling in Heterogeneous Three-Dimensional ICs - p. 119 15. Chapter 6. Three-Dimensional ICs with Inductive Links - p. 137 16. Chapter 7. Interconnect Prediction Models - p. 163 17. Chapter 8. Cost Considerations for Three-Dimensional Integration - p. 175 18. Chapter 9. Physical Design Techniques for Three-Dimensional ICs - p. 203 19. Chapter 10. Timing Optimization for Two-Terminal Interconnects - p. 253 20. Chapter 11. Timing Optimization for Multiterminal Interconnects - p. 281 21. Chapter 12. Thermal Modeling and Analysis - p. 295 22. Chapter 13. Thermal Management Strategies for Three-Dimensional ICs - p. 333 23. Chapter 14. Case Study: Thermal Coupling in 3-D Integrated Circuits - p. 381 24. Chapter 15. Synchronization in Three-Dimensional ICs - p. 409 25. Chapter 16. Case Study: Clock Distribution Networks for Three-Dimensional ICs - p. 449 26. Chapter 17. Variability Issues in Three-Dimensional ICs - p. 475 27. Abstract - p. 475 28. 17.1 Process Variations in Data paths Within Three-Dimensional ICs - p. 477 29. 17.2 Effects of Process Variations on Clock Paths - p. 482 30. 17.3 Effect of Process and Power Supply Variations on Three-Dimensional Clock Distribution Networks - p. 495 31. 17.4 Summary - p. 517 32. Chapter 18. Power Delivery for Three-Dimensional ICs - p. 519 33. Chapter 19. Case Study: 3-D Power Distribution Topologies and Models - p. 565 34. Chapter 20. 3-D Circuit Architectures - p. 605 35. Chapter 21. Conclusions - p. 649 36. Appendix A. Enumeration of Gate Pairs in a 3-D IC - p. 653 37. Appendix B. Formal Proof of Optimum Single Via Placement - p. 655 38. Appendix C. Proof of the Two-Terminal Via Placement Heuristic - p. 657 39. Appendix D. Proof of Condition for Via Placement of Multi-terminal Nets - p. 659 40. Appendix E. Correlation of WID Variations for Intratier Buffers - p. 661 41. Appendix F. Extension of the Proposed Model to Include Variations of Wires - p. 663 42. Glossary of Terms - p. 665 43. References - p. 669 44. Index - p. 709
Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more than twice as much new content, adding the latest developments in circuit models, temperature considerations, power management, memory issues, and heterogeneous integration. 3-D IC experts Pavlidis, Savidis, and Friedman cover the full product development cycle throughout the book, emphasizing not only physical design, but also algorithms and system-level considerations to increase speed while conserving energy. A handy, comprehensive reference or a practical design guide, this book provides effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits.
Expanded with new chapters and updates throughout based on the latest research in 3-D integration:
1. Chapter 1. Introduction - p. 1 2. Chapter 2. Manufacturing of Three-Dimensional Packaged Systems - p. 15 3. Chapter 3. Manufacturing Technologies for Three-Dimensional Integrated Circuits - p. 37 4. Chapter 4. Electrical Properties of Through Silicon Vias - p. 67 5. Abstract - p. 67 6. 4.1 Physical Characteristics of a Through Silicon Via - p. 69 7. 4.2 Electrical Model of Through Silicon Via - p. 70 8. 4.3 Modeling a Three-Dimensional Via as a Cylinder - p. 71 9. 4.4 Compact Models - p. 73 10. 4.5 Through Silicon Via Impedance Models - p. 82 11. 4.6 Electrical Characterization Through Numerical Simulation - p. 105 12. 4.7 Case Study—Through Silicon Via Characterization of the MITLL TSV process - p. 107 13. 4.8 Summary - p. 116 14. Chapter 5. Substrate Noise Coupling in Heterogeneous Three-Dimensional ICs - p. 119 15. Chapter 6. Three-Dimensional ICs with Inductive Links - p. 137 16. Chapter 7. Interconnect Prediction Models - p. 163 17. Chapter 8. Cost Considerations for Three-Dimensional Integration - p. 175 18. Chapter 9. Physical Design Techniques for Three-Dimensional ICs - p. 203 19. Chapter 10. Timing Optimization for Two-Terminal Interconnects - p. 253 20. Chapter 11. Timing Optimization for Multiterminal Interconnects - p. 281 21. Chapter 12. Thermal Modeling and Analysis - p. 295 22. Chapter 13. Thermal Management Strategies for Three-Dimensional ICs - p. 333 23. Chapter 14. Case Study: Thermal Coupling in 3-D Integrated Circuits - p. 381 24. Chapter 15. Synchronization in Three-Dimensional ICs - p. 409 25. Chapter 16. Case Study: Clock Distribution Networks for Three-Dimensional ICs - p. 449 26. Chapter 17. Variability Issues in Three-Dimensional ICs - p. 475 27. Abstract - p. 475 28. 17.1 Process Variations in Data paths Within Three-Dimensional ICs - p. 477 29. 17.2 Effects of Process Variations on Clock Paths - p. 482 30. 17.3 Effect of Process and Power Supply Variations on Three-Dimensional Clock Distribution Networks - p. 495 31. 17.4 Summary - p. 517 32. Chapter 18. Power Delivery for Three-Dimensional ICs - p. 519 33. Chapter 19. Case Study: 3-D Power Distribution Topologies and Models - p. 565 34. Chapter 20. 3-D Circuit Architectures - p. 605 35. Chapter 21. Conclusions - p. 649 36. Appendix A. Enumeration of Gate Pairs in a 3-D IC - p. 653 37. Appendix B. Formal Proof of Optimum Single Via Placement - p. 655 38. Appendix C. Proof of the Two-Terminal Via Placement Heuristic - p. 657 39. Appendix D. Proof of Condition for Via Placement of Multi-terminal Nets - p. 659 40. Appendix E. Correlation of WID Variations for Intratier Buffers - p. 661 41. Appendix F. Extension of the Proposed Model to Include Variations of Wires - p. 663 42. Glossary of Terms - p. 665 43. References - p. 669 44. Index - p. 709
