Computer Architecture: A Quantitative Approach, Sixth Edition has been considered essential reading by instructors, students and practitioners of computer design for over 20 years. The sixth edition of this classic textbook from Hennessy and Patterson, winners of the 2017 ACM A.M. Turing Award recognizing contributions of lasting and major technical importance to the computing field, is fully revised with the latest developments in processor and system architecture. The text now features examples from the RISC-V (RISC Five) instruction set architecture, a modern RISC instruction set developed and designed to be a free and openly adoptable standard. It also includes a new chapter on domain-specific architectures and an updated chapter on warehouse-scale computing that features the first public information on Google's newest WSC.
True to its original mission of demystifying computer architecture, this edition continues the longstanding tradition of focusing on areas where the most exciting computing innovation is happening, while always keeping an emphasis on good engineering design.
1. 5.1 Introduction - p. 368 2. 5.2 Centralized Shared-Memory Architectures - p. 377 3. 5.3 Performance of Symmetric Shared-Memory Multiprocessors - p. 393 4. 5.4 Distributed Shared-Memory and Directory-Based Coherence - p. 404 5. 5.5 Synchronization: The Basics - p. 412 6. 5.6 Models of Memory Consistency: An Introduction - p. 417 7. 5.7 Cross-Cutting Issues - p. 422 8. 5.8 Putting It All Together: Multicore Processors and Their Performance - p. 426 9. 5.9 Fallacies and Pitfalls - p. 437 10. 5.10 The Future of Multicore Scaling - p. 442 11. 5.11 Concluding Remarks - p. 444 12. 5.12 Historical Perspectives and References - p. 446 13. Case Studies and Exercises by Amr Zaky and David A. Wood - p. 446 14. References - p. 462 15. 6. Warehouse-Scale Computers to Exploit Request-Level and Data-Level Parallelism - p. 464 16. 7. Domain-Specific Architectures - p. 539 17. Appendix A. Instruction Set Principles - p. A-0 18. Appendix B. Review of Memory Hierarchy - p. B-0 19. Appendix C. Pipelining: Basic and Intermediate Concepts - p. C-0 20. Appendix D. Storage Systems - p. D-0 21. Appendix E. Embedded Systems - p. E-0 22. Appendix F. Interconnection Networks - p. F-1 23. F.1 Introduction - p. F-2 24. F.2 Interconnecting Two Devices - p. F-6 25. F.3 Connecting More than Two Devices - p. F-20 26. F.4 Network Topology - p. F-30 27. F.5 Network Routing, Arbitration, and Switching - p. F-43 28. F.6 Switch Microarchitecture - p. F-55 29. F.7 Practical Issues for Commercial Interconnection Networks - p. F-66 30. F.8 Examples of Interconnection Networks - p. F-73 31. F.9 Internetworking - p. F-85 32. F.10 Crosscutting Issues for Interconnection Networks - p. F-89 33. F.11 Fallacies and Pitfalls - p. F-92 34. F.12 Concluding Remarks - p. F-100 35. F.13 Historical Perspective and References - p. F-101 36. Exercises - p. F-109 37. References - p. F-118 38. Appendix G. Vector Processors in More Depth - p. G-1 39. Appendix H. Hardware and Software for VLIW and EPIC - p. H-0 40. Appendix I. Large-Scale Multiprocessors and Scientific Applications - p. I-0 41. Appendix J. Computer Arithmetic - p. J-59 42. J.1 Introduction - p. J-2 43. J.2 Basic Techniques of Integer Arithmetic - p. J-2 44. J.3 Floating Point - p. J-13 45. J.4 Floating-Point Multiplication - p. J-16 46. J.5 Floating-Point Addition - p. J-21 47. J.6 Division and Remainder - p. J-27 48. J.7 More on Floating-Point Arithmetic - p. J-32 49. J.8 Speeding Up Integer Addition - p. J-37 50. J.9 Speeding Up Integer Multiplication and Division - p. J-44 51. J.10 Putting It All Together - p. J-57 52. J.11 Fallacies and Pitfalls - p. J-62 53. J.12 Historical Perspective and References - p. J-63 54. Exercises - p. J-65 55. References - p. J-73 56. Appendix K. Survey of Instruction Set Architectures - p. K-0 57. Appendix L. Advanced Concepts on Address Translation - p. K-74 58. Appendix M. Historical Perspectives and References - p. M-1 59. M.1 Introduction - p. M-2 60. M.2 The Early Development of Computers (Chapter 1) - p. M-2 61. References - p. M-7 62. M.3 The Development of Memory Hierarchy and Protection (Chapter 2 and Appendix B) - p. M-9 63. References - p. M-12 64. M.4 The Evolution of Instruction Sets (Appendices A, J, and K) - p. M-17 65. References - p. M-23 66. M.5 The Development of Pipelining and Instruction-Level Parallelism (Chapter 3 and Appendices C and H) - p. M-27 67. References - p. M-36 68. M.6 The Development of SIMD Supercomputers, Vector Computers, Multimedia SIMD Instruction Extensions, and Graphical Processor Units (Chapter 4) - p. M-45 69. References - p. M-53 70. M.7 The History of Multiprocessors and Parallel Processing (Chapter 5 and Appendices F, G, and I) - p. M-55 71. References - p. M-65 72. M.8 The Development of Clusters (Chapter 6) - p. M-74 73. References - p. M-76 74. M.9 Historical Perspectives and References - p. M-79 75. References - p. M-80 76. M.10 The History of Magnetic Storage, RAID, and I/O Buses (Appendix D) - p. M-84 77. References - p. M-89 78. References - p. M-93 79. Index - p. M-93 80. Back End Sheet - p. M-93 81. Inside Back Cover - p. M-93
Computer Architecture: A Quantitative Approach, Sixth Edition has been considered essential reading by instructors, students and practitioners of computer design for over 20 years. The sixth edition of this classic textbook from Hennessy and Patterson, winners of the 2017 ACM A.M. Turing Award recognizing contributions of lasting and major technical importance to the computing field, is fully revised with the latest developments in processor and system architecture. The text now features examples from the RISC-V (RISC Five) instruction set architecture, a modern RISC instruction set developed and designed to be a free and openly adoptable standard. It also includes a new chapter on domain-specific architectures and an updated chapter on warehouse-scale computing that features the first public information on Google's newest WSC.
True to its original mission of demystifying computer architecture, this edition continues the longstanding tradition of focusing on areas where the most exciting computing innovation is happening, while always keeping an emphasis on good engineering design.
1. 5.1 Introduction - p. 368 2. 5.2 Centralized Shared-Memory Architectures - p. 377 3. 5.3 Performance of Symmetric Shared-Memory Multiprocessors - p. 393 4. 5.4 Distributed Shared-Memory and Directory-Based Coherence - p. 404 5. 5.5 Synchronization: The Basics - p. 412 6. 5.6 Models of Memory Consistency: An Introduction - p. 417 7. 5.7 Cross-Cutting Issues - p. 422 8. 5.8 Putting It All Together: Multicore Processors and Their Performance - p. 426 9. 5.9 Fallacies and Pitfalls - p. 437 10. 5.10 The Future of Multicore Scaling - p. 442 11. 5.11 Concluding Remarks - p. 444 12. 5.12 Historical Perspectives and References - p. 446 13. Case Studies and Exercises by Amr Zaky and David A. Wood - p. 446 14. References - p. 462 15. 6. Warehouse-Scale Computers to Exploit Request-Level and Data-Level Parallelism - p. 464 16. 7. Domain-Specific Architectures - p. 539 17. Appendix A. Instruction Set Principles - p. A-0 18. Appendix B. Review of Memory Hierarchy - p. B-0 19. Appendix C. Pipelining: Basic and Intermediate Concepts - p. C-0 20. Appendix D. Storage Systems - p. D-0 21. Appendix E. Embedded Systems - p. E-0 22. Appendix F. Interconnection Networks - p. F-1 23. F.1 Introduction - p. F-2 24. F.2 Interconnecting Two Devices - p. F-6 25. F.3 Connecting More than Two Devices - p. F-20 26. F.4 Network Topology - p. F-30 27. F.5 Network Routing, Arbitration, and Switching - p. F-43 28. F.6 Switch Microarchitecture - p. F-55 29. F.7 Practical Issues for Commercial Interconnection Networks - p. F-66 30. F.8 Examples of Interconnection Networks - p. F-73 31. F.9 Internetworking - p. F-85 32. F.10 Crosscutting Issues for Interconnection Networks - p. F-89 33. F.11 Fallacies and Pitfalls - p. F-92 34. F.12 Concluding Remarks - p. F-100 35. F.13 Historical Perspective and References - p. F-101 36. Exercises - p. F-109 37. References - p. F-118 38. Appendix G. Vector Processors in More Depth - p. G-1 39. Appendix H. Hardware and Software for VLIW and EPIC - p. H-0 40. Appendix I. Large-Scale Multiprocessors and Scientific Applications - p. I-0 41. Appendix J. Computer Arithmetic - p. J-59 42. J.1 Introduction - p. J-2 43. J.2 Basic Techniques of Integer Arithmetic - p. J-2 44. J.3 Floating Point - p. J-13 45. J.4 Floating-Point Multiplication - p. J-16 46. J.5 Floating-Point Addition - p. J-21 47. J.6 Division and Remainder - p. J-27 48. J.7 More on Floating-Point Arithmetic - p. J-32 49. J.8 Speeding Up Integer Addition - p. J-37 50. J.9 Speeding Up Integer Multiplication and Division - p. J-44 51. J.10 Putting It All Together - p. J-57 52. J.11 Fallacies and Pitfalls - p. J-62 53. J.12 Historical Perspective and References - p. J-63 54. Exercises - p. J-65 55. References - p. J-73 56. Appendix K. Survey of Instruction Set Architectures - p. K-0 57. Appendix L. Advanced Concepts on Address Translation - p. K-74 58. Appendix M. Historical Perspectives and References - p. M-1 59. M.1 Introduction - p. M-2 60. M.2 The Early Development of Computers (Chapter 1) - p. M-2 61. References - p. M-7 62. M.3 The Development of Memory Hierarchy and Protection (Chapter 2 and Appendix B) - p. M-9 63. References - p. M-12 64. M.4 The Evolution of Instruction Sets (Appendices A, J, and K) - p. M-17 65. References - p. M-23 66. M.5 The Development of Pipelining and Instruction-Level Parallelism (Chapter 3 and Appendices C and H) - p. M-27 67. References - p. M-36 68. M.6 The Development of SIMD Supercomputers, Vector Computers, Multimedia SIMD Instruction Extensions, and Graphical Processor Units (Chapter 4) - p. M-45 69. References - p. M-53 70. M.7 The History of Multiprocessors and Parallel Processing (Chapter 5 and Appendices F, G, and I) - p. M-55 71. References - p. M-65 72. M.8 The Development of Clusters (Chapter 6) - p. M-74 73. References - p. M-76 74. M.9 Historical Perspectives and References - p. M-79 75. References - p. M-80 76. M.10 The History of Magnetic Storage, RAID, and I/O Buses (Appendix D) - p. M-84 77. References - p. M-89 78. References - p. M-93 79. Index - p. M-93 80. Back End Sheet - p. M-93 81. Inside Back Cover - p. M-93
