Computer Organization and Design RISC-V Edition: The Hardware Software Interface, Second Edition, the award-winning textbook from Patterson and Hennessy that is used by more than 40,000 students per year, continues to present the most comprehensive and readable introduction to this core computer science topic. This version of the book features the RISC-V open source instruction set architecture, the first open source architecture designed for use in modern computing environments such as cloud computing, mobile devices, and other embedded systems. Readers will enjoy an online companion website that provides advanced content for further study, appendices, glossary, references, links to software tools, and more.
1. 1.1: Introduction - p. 3 2. 1.2: Seven Great Ideas in Computer Architecture - p. 10 3. 1.3: Below Your Program - p. 13 4. 1.4: Under the Covers - p. 16 5. 1.5: Technologies for Building Processors and Memory - p. 25 6. 1.6: Performance - p. 29 7. 1.7: The Power Wall - p. 40 8. 1.8: The Sea Change: The Switch from Uniprocessors to Multiprocessors - p. 43 9. 1.9: Real Stuff: Benchmarking the Intel Core i7 - p. 46 10. 1.10: Going Faster: Matrix Multiply in Python - p. 49 11. 1.11: Fallacies and Pitfalls - p. 50 12. 1.12: Concluding Remarks - p. 53 13. 1.13: Historical Perspective and Further Reading - p. 54.e1 14. Historical Perspective and Further Reading - p. 54.e1 15. 2 Instructions - p. 66 16. 2.1: Introduction - p. 68 17. 2.2: Operations of the Computer Hardware - p. 69 18. 2.3: Operands of the Computer Hardware - p. 73 19. 2.4: Signed and Unsigned Numbers - p. 80 20. 2.5: Representing Instructions in the Computer - p. 87 21. 2.6: Logical Operations - p. 95 22. 2.7: Instructions for Making Decisions - p. 98 23. 2.8: Supporting Procedures in Computer Hardware - p. 104 24. 2.9: Communicating with People - p. 114 25. 2.10: RISC-V Addressing for Wide Immediates and Addresses - p. 120 26. 2.11: Parallelism and Instructions: Synchronization - p. 128 27. 2.12: Translating and Starting a Program - p. 131 28. 2.13: A C Sort Example to Put it All Together - p. 140 29. 2.14: Arrays versus Pointers - p. 148 30. Advanced Material: Compiling C and Interpreting Java - p. 151 31. Advanced Material: Compiling C and Interpreting Java - p. 152 32. 2.16: Real Stuff: MIPS Instructions - p. 152 33. 2.17: Real Stuff: ARMv7 (32-bit) Instructions - p. 154 34. 2.18: Real Stuff: ARMv8 (64-bit) Instructions - p. 157 35. 2.19: Real Stuff: x86 Instructions - p. 158 36. 2.20: Real Stuff: The Rest of the RISC-V Instruction Set - p. 167 37. 2.21: Going Faster: Matrix Multiply in C - p. 168 38. 2.22: Fallacies and Pitfalls - p. 170 39. 2.23: Concluding Remarks - p. 172 40. Historical Perspective and Further Reading - p. 174 41. Historical Perspective and Further Reading - p. 175 42. 3 Arithmetic for Computers - p. 188 43. 4 The Processor - p. 252 44. 4.1: Introduction - p. 254 45. 4.2: Logic Design Conventions - p. 258 46. 4.3: Building a Datapath - p. 261 47. 4.4: A Simple Implementation Scheme - p. 269 48. A Multicycle Implementation - p. 282 49. A Multicycle Implementation - p. 283 50. 4.6: An Overview of Pipelining - p. 282.e20 51. 4.7: Pipelined Datapath and Control - p. 296 52. 4.8: Data Hazards: Forwarding versus Stalling - p. 313 53. 4.9: Control Hazards - p. 325 54. 4.10: Exceptions - p. 333 55. 4.11: Parallelism via Instructions - p. 340 56. 4.12: Putting It All Together: The Intel Core i7 6700 and ARM Cortex-A53 - p. 354 57. 4.13: Going Faster: Instruction-Level Parallelism and Matrix Multiply - p. 363 58. Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations - p. 365 59. 4.15: Fallacies and Pitfalls - p. 365 60. Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations - p. 367 61. 4.16: Concluding Remarks - p. 367 62. Historical Perspective and Further Reading - p. 368 63. Historical Perspective and Further Reading - p. 368 64. 5 Large and Fast - p. 386 65. 5.1: Introduction - p. 388 66. 5.2: Memory Technologies - p. 392 67. 5.3: The Basics of Caches - p. 398 68. 5.4: Measuring and Improving Cache Performance - p. 412 69. 5.5: Dependable Memory Hierarchy - p. 431 70. 5.6: Virtual Machines - p. 436 71. 5.7: Virtual Memory - p. 440 72. 5.8: A Common Framework for Memory Hierarchy - p. 464 73. 5.9: Using a Finite-State Machine to Control a Simple Cache - p. 470 74. 5.10: Parallelism and Memory Hierarchy: Cache Coherence - p. 475 75. Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive Disks - p. 479 76. Performance of the Cortex-A53 and Core i7 Memory Hierarchies - p. 483 77. 5.14: Real Stuff: The Rest of the RISC-V System and Special Instructions - p. 486 78. 5.15: Going Faster: Cache Blocking and Matrix Multiply - p. 488 79. 5.16: Fallacies and Pitfalls - p. 489 80. 5.17: Concluding Remarks - p. 494 81. Historical Perspective and Further Reading - p. 495 82. 6 Parallel Processors from Client to Cloud - p. 518 83. 6.1: Introduction - p. 520 84. 6.2: The Difficulty of Creating Parallel Processing Programs - p. 522 85. 6.3: SISD, MIMD, SIMD, SPMD, and Vector - p. 527 86. 6.4: Hardware Multithreading - p. 534 87. 6.5: Multicore and Other Shared Memory Multiprocessors - p. 537 88. 6.6: Introduction to Graphics Processing Units - p. 542 89. 6.7: Domain-Specific Architectures - p. 549 90. 6.8: Clusters, Warehouse Scale Computers, and Other Message-Passing Multiprocessors - p. 552 91. 6.9: Introduction to Multiprocessor Network Topologies - p. 557 92. Communicating to the Outside World: Cluster Networking - p. 561 93. Communicating to the Outside World: Cluster Networking - p. 561 94. 6.11: Multiprocessor Benchmarks and Performance Models - p. 561 95. 6.12: Real Stuff: Benchmarking the Google TPUv3 Supercomputer and an NVIDIA Volta GPU Cluster - p. 572 96. 6.13: Going Faster: Multiple Processors and Matrix Multiply - p. 580 97. 6.14: Fallacies and Pitfalls - p. 583 98. 6.15: Concluding Remarks - p. 585 99. Historical Perspective and Further Reading - p. 587 100. Historical Perspective and Further Reading - p. 588 101. APPENDIX A The Basics of Logic Design - p. A-2 102. APPENDIX B Graphics and Computing GPUs - p. B-2 103. APPENDIX C Mapping Control to Hardware - p. C-2 104. APPENDIX D Survey of Instruction Set Architectures - p. D-2 105. Reference Data - p. ES1 106. Further Reading - p. FR-1 107. Answers to Check Yourself - p. e-1 108. Glossary - p. G-1 109. Index - p. I-1
Computer Organization and Design RISC-V Edition: The Hardware Software Interface, Second Edition, the award-winning textbook from Patterson and Hennessy that is used by more than 40,000 students per year, continues to present the most comprehensive and readable introduction to this core computer science topic. This version of the book features the RISC-V open source instruction set architecture, the first open source architecture designed for use in modern computing environments such as cloud computing, mobile devices, and other embedded systems. Readers will enjoy an online companion website that provides advanced content for further study, appendices, glossary, references, links to software tools, and more.
1. 1.1: Introduction - p. 3 2. 1.2: Seven Great Ideas in Computer Architecture - p. 10 3. 1.3: Below Your Program - p. 13 4. 1.4: Under the Covers - p. 16 5. 1.5: Technologies for Building Processors and Memory - p. 25 6. 1.6: Performance - p. 29 7. 1.7: The Power Wall - p. 40 8. 1.8: The Sea Change: The Switch from Uniprocessors to Multiprocessors - p. 43 9. 1.9: Real Stuff: Benchmarking the Intel Core i7 - p. 46 10. 1.10: Going Faster: Matrix Multiply in Python - p. 49 11. 1.11: Fallacies and Pitfalls - p. 50 12. 1.12: Concluding Remarks - p. 53 13. 1.13: Historical Perspective and Further Reading - p. 54.e1 14. Historical Perspective and Further Reading - p. 54.e1 15. 2 Instructions - p. 66 16. 2.1: Introduction - p. 68 17. 2.2: Operations of the Computer Hardware - p. 69 18. 2.3: Operands of the Computer Hardware - p. 73 19. 2.4: Signed and Unsigned Numbers - p. 80 20. 2.5: Representing Instructions in the Computer - p. 87 21. 2.6: Logical Operations - p. 95 22. 2.7: Instructions for Making Decisions - p. 98 23. 2.8: Supporting Procedures in Computer Hardware - p. 104 24. 2.9: Communicating with People - p. 114 25. 2.10: RISC-V Addressing for Wide Immediates and Addresses - p. 120 26. 2.11: Parallelism and Instructions: Synchronization - p. 128 27. 2.12: Translating and Starting a Program - p. 131 28. 2.13: A C Sort Example to Put it All Together - p. 140 29. 2.14: Arrays versus Pointers - p. 148 30. Advanced Material: Compiling C and Interpreting Java - p. 151 31. Advanced Material: Compiling C and Interpreting Java - p. 152 32. 2.16: Real Stuff: MIPS Instructions - p. 152 33. 2.17: Real Stuff: ARMv7 (32-bit) Instructions - p. 154 34. 2.18: Real Stuff: ARMv8 (64-bit) Instructions - p. 157 35. 2.19: Real Stuff: x86 Instructions - p. 158 36. 2.20: Real Stuff: The Rest of the RISC-V Instruction Set - p. 167 37. 2.21: Going Faster: Matrix Multiply in C - p. 168 38. 2.22: Fallacies and Pitfalls - p. 170 39. 2.23: Concluding Remarks - p. 172 40. Historical Perspective and Further Reading - p. 174 41. Historical Perspective and Further Reading - p. 175 42. 3 Arithmetic for Computers - p. 188 43. 4 The Processor - p. 252 44. 4.1: Introduction - p. 254 45. 4.2: Logic Design Conventions - p. 258 46. 4.3: Building a Datapath - p. 261 47. 4.4: A Simple Implementation Scheme - p. 269 48. A Multicycle Implementation - p. 282 49. A Multicycle Implementation - p. 283 50. 4.6: An Overview of Pipelining - p. 282.e20 51. 4.7: Pipelined Datapath and Control - p. 296 52. 4.8: Data Hazards: Forwarding versus Stalling - p. 313 53. 4.9: Control Hazards - p. 325 54. 4.10: Exceptions - p. 333 55. 4.11: Parallelism via Instructions - p. 340 56. 4.12: Putting It All Together: The Intel Core i7 6700 and ARM Cortex-A53 - p. 354 57. 4.13: Going Faster: Instruction-Level Parallelism and Matrix Multiply - p. 363 58. Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations - p. 365 59. 4.15: Fallacies and Pitfalls - p. 365 60. Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations - p. 367 61. 4.16: Concluding Remarks - p. 367 62. Historical Perspective and Further Reading - p. 368 63. Historical Perspective and Further Reading - p. 368 64. 5 Large and Fast - p. 386 65. 5.1: Introduction - p. 388 66. 5.2: Memory Technologies - p. 392 67. 5.3: The Basics of Caches - p. 398 68. 5.4: Measuring and Improving Cache Performance - p. 412 69. 5.5: Dependable Memory Hierarchy - p. 431 70. 5.6: Virtual Machines - p. 436 71. 5.7: Virtual Memory - p. 440 72. 5.8: A Common Framework for Memory Hierarchy - p. 464 73. 5.9: Using a Finite-State Machine to Control a Simple Cache - p. 470 74. 5.10: Parallelism and Memory Hierarchy: Cache Coherence - p. 475 75. Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive Disks - p. 479 76. Performance of the Cortex-A53 and Core i7 Memory Hierarchies - p. 483 77. 5.14: Real Stuff: The Rest of the RISC-V System and Special Instructions - p. 486 78. 5.15: Going Faster: Cache Blocking and Matrix Multiply - p. 488 79. 5.16: Fallacies and Pitfalls - p. 489 80. 5.17: Concluding Remarks - p. 494 81. Historical Perspective and Further Reading - p. 495 82. 6 Parallel Processors from Client to Cloud - p. 518 83. 6.1: Introduction - p. 520 84. 6.2: The Difficulty of Creating Parallel Processing Programs - p. 522 85. 6.3: SISD, MIMD, SIMD, SPMD, and Vector - p. 527 86. 6.4: Hardware Multithreading - p. 534 87. 6.5: Multicore and Other Shared Memory Multiprocessors - p. 537 88. 6.6: Introduction to Graphics Processing Units - p. 542 89. 6.7: Domain-Specific Architectures - p. 549 90. 6.8: Clusters, Warehouse Scale Computers, and Other Message-Passing Multiprocessors - p. 552 91. 6.9: Introduction to Multiprocessor Network Topologies - p. 557 92. Communicating to the Outside World: Cluster Networking - p. 561 93. Communicating to the Outside World: Cluster Networking - p. 561 94. 6.11: Multiprocessor Benchmarks and Performance Models - p. 561 95. 6.12: Real Stuff: Benchmarking the Google TPUv3 Supercomputer and an NVIDIA Volta GPU Cluster - p. 572 96. 6.13: Going Faster: Multiple Processors and Matrix Multiply - p. 580 97. 6.14: Fallacies and Pitfalls - p. 583 98. 6.15: Concluding Remarks - p. 585 99. Historical Perspective and Further Reading - p. 587 100. Historical Perspective and Further Reading - p. 588 101. APPENDIX A The Basics of Logic Design - p. A-2 102. APPENDIX B Graphics and Computing GPUs - p. B-2 103. APPENDIX C Mapping Control to Hardware - p. C-2 104. APPENDIX D Survey of Instruction Set Architectures - p. D-2 105. Reference Data - p. ES1 106. Further Reading - p. FR-1 107. Answers to Check Yourself - p. e-1 108. Glossary - p. G-1 109. Index - p. I-1
